Saturday, June 20

Workshops and Tutorials

Session I

• WEED: Workshop on Energy Efficient Design , Meeting Room 406
• WIOSCA: Workshop on Interaction betweeen Operating System and Computer Architecture , Meeting Room 408
• WARP: Workshop on Architectural Research Prototyping , Meeting Room 410
• AMAS-BT: Workshop on Architectural and Micro-Architectural Support for Binary Translation , Meeting Room 412
• BiC: Workshop on Biomedicine in Computing: Systems, Architectures, and Circuits , Meeting Room 602

Session II

• WEED: Workshop on Energy Efficient Design , Meeting Room 406
• WIOSCA: Workshop on Interaction betweeen Operating System and Computer Architecture , Meeting Room 408
• WARP: Workshop on Architectural Research Prototyping , Meeting Room 410
• AMAS-BT: Workshop on Architectural and Micro-Architectural Support for Binary Translation , Meeting Room 412
• BiC: Workshop on Biomedicine in Computing: Systems, Architectures, and Circuits , Meeting Room 602

Session III

• WEED: Workshop on Energy Efficient Design , Meeting Room 406
• WIOSCA: Workshop on Interaction betweeen Operating System and Computer Architecture , Meeting Room 408
• WARP: Workshop on Architectural Research Prototyping , Meeting Room 410
• CMP-MSI: Workshop on Chip Multiprocessor Memory Systems and Interconnects , Meeting Room 412
• FutMEM: Scalability Challenges for Future Memory Subsystems , Meeting Room 602

Session IV

• WEED: Workshop on Energy Efficient Design , Meeting Room 406
• WIOSCA: Workshop on Interaction betweeen Operating System and Computer Architecture , Meeting Room 408
• WARP: Workshop on Architectural Research Prototyping , Meeting Room 410
• CMP-MSI: Workshop on Chip Multiprocessor Memory Systems and Interconnects , Meeting Room 412
• FutMEM: Scalability Challenges for Future Memory Subsystems , Meeting Room 602

Sunday, June 21

Workshops and Tutorials

Session I

• ACLD: Architectural Concerns in Large Datacenters Meeting Room 406
• PESPMA: Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures Meeting Room 408
• MoBS: Workshop on Modeling, Benchmarking and Simulation Meeting Room 410
• WEMT: Workshop on Emerging Memory Technologies Meeting Room 412
• ADSE: Tutorial on Architectural Design for Soft Errors Meeting Room 404

Session II

• ACLD: Architectural Concerns in Large Datacenters Meeting Room 406
• PESPMA: Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures Meeting Room 408
• MoBS: Workshop on Modeling, Benchmarking and Simulation Meeting Room 410
• WEMT: Workshop on Emerging Memory Technologies Meeting Room 412
• ADSE: Tutorial on Architectural Design for Soft Errors Meeting Room 404

Session III

• CARD: Workshop on Computer Architecture Research Directions Meeting Room 406
• PESPMA: Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures Meeting Room 408
• WDDD: Workshop on Duplicating, Deconstructing and Debunking Meeting Room 410
• WEMT: Workshop on Emerging Memory Technologies Meeting Room 412
• MASD: Tutorial on Manageability-Aware Systems Design Meeting Room 404

Session IV

• CARD: Workshop on Computer Architecture Research Directions Meeting Room 406
• PESPMA: Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures Meeting Room 408
• WDDD: Workshop on Duplicating, Deconstructing and Debunking Meeting Room 410
• WEMT: Workshop on Emerging Memory Technologies Meeting Room 412
• MASD: Tutorial on Manageability-Aware Systems Design Meeting Room 404

Reception

Monday, June 22

Main Conference Program

Opening Remarks

Keynote I: Ten Ways to Waste a Parallel Computer

Session 1: New Memory Technology

• Architecting Phase Change Memory as a Scalable DRAM Alternative (Presentation)
  Benjamin C. Lee, Engin Ipek (Microsoft Research ), Onur Mutlu (Carnegie Mellon University), Doug Burger (Microsoft Research)


• A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology
  Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang (University of Pittsburgh)


• Scalable High Performance Main Memory System Using Phase-Change Memory Technology (Presentation)
  Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers (IBM T.J. Watson Research Center)


• Hybrid Cache Architecture with Disparate Memory Technologies (Presentation)
  Xiaoxia Wu (The Pennsylvania State University), Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony (IBM Austin Research Laboratory), Yuan Xie (The Pennsylvania State University)

Session 2A: Real Time

• Dynamic MIPS Rate Stabilization in Out-of-Order Processors (Presentation)
  Jinho Suh, Michel Dubois (University of Southern California)


• Hardware Support for WCET Analysis of Hard Real-Time Multicore Systems (Presentation)
  Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla (Barcelona Supercomputing Center), Guillem Bernat (Rapita System Ltd.), Mateo Valero (Universitat Politècnica de Catalunya and BSC)

Session 2B: Prefetching and Streaming

• Spatio-Temporal Memory Streaming
  Stephen Somogyi (Carnegie Mellon University), Thomas F. Wenisch (University of Michigan), Anastasia Ailamaki (École Polytechnique Fédérale de Lausanne & Carnegie Mellon University), Babak Falsafi (École Polytechnique Fédérale de Lausanne)
(Presentation)

• Stream Chaining: Exploiting Multiple Levels of Correlation in Data Prefetching
  Pedro Díaz, Marcelo Cintra (University of Edinburgh)

(Presentation)

Session 3A: Reliability and Fault Tolerance

• Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance (Presentation)
  Michael D. Powell, Arijit Biswas (Intel Massachusetts), Shantanu Gupta (University of Michigan), Shubhendu S. Mukherjee (Intel Massachusetts)


• End-to-End Register Data-Flow Continuous Self-Test
  Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González (Intel Barcelona Research Center)


• Memory Mapped ECC: Low-Cost Error Protection for Last Level Caches (Presentation)
  Doe Hyun Yoon, Mattan Erez (University of Texas at Austin)

Session 3B: Multimedia and Mobile

• AnySP: Anytime Anywhere Anyway Signal Processing
  Mark Who, Sangwon Seo, Scott Mahlke, Trevor Mudge (University of Michigan), Chaitali Chakrabarti (Arizona State University), Krisztian Flautner (ARM, Ltd.)


• Rigel: An Architecture and Scalable Programming Interface for a 1000-core Accelerator (Presentation)
  John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal C. Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel (University of Illinois at Urbana-Champaign)


• An Analytical Model for a GPU Architecture with Memory-level and Thread-level Parallelism Awareness (Presentation)
  Sunpyo Hong, Hyesoon Kim (Georgia Institute of Technology)

Session 4A: Cache Organization

• Multi-Execution: Multicore Caching for Data-Similar Executions (Presentation)
  Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong (University of California, Santa Barbara)


• PIPP: Promotion/Insertion Pseudo-Partitioning of Multi-Core Shared Caches (Presentation)
  Yuejian Xie, Gabriel H. Loh (Georgia Institute of Technology)


• Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches (Presentation)
  Nikos Hardavellas (Carnegie Mellon University), Michael Ferdman (Carnegie Mellon University & École Polytechnique Fédérale de Lausanne), Babak Falsafi (École Polytechnique Fédérale de Lausanne), Anastasia Ailamaki (École Polytechnique Fédérale de Lausanne & Carnegie Mellon University)

Session 4B: Routing

• A Case for Bufferless Routing in On-Chip Networks (Presentation)
  Thomas Moscibroda (Microsoft Research), Onur Mutlu (Carnegie Mellon University)


• Application-Aware Deadlock-Free Oblivious Routing (Presentation)
  Michel Kinsy, Myong Hyon Cho, Tina Wen (Massachusetts Institute of Technology), Edward Suh (Cornell University), Marten van Dijk, Srinivas Devadas (Massachusetts Institute of Technology)


• Indirect Adaptive Routing on Large Scale Interconnection Networks (Presentation)
  Nan Jiang (Stanford University), John Kim (KAIST), William J. Dally (Stanford University)

Business Meeting

Tuesday, June 23

Keynote II: Internet-Scale Service Infrastructure Efficiency

Session 5: Load and Stores

• InvisiFENCE: Performance-Transparent Memory Ordering in Conventional Multiprocessors (Presentation)
  Colin Blundell, Milo M. K. Martin (The University of Pennsylvania), Thomas F. Wenisch (University of Michigan)


• Decoupled Store Completion/Silent Deterministic Replay: Enabling Scalable Data Memory for CPR/CFP Processors (ppt)
  Andrew Hilton, Amir Roth (The University of Pennsylvania)

Session 6: DRAM and SSD

• Decoupled DIMM: Building High-Bandwidth Memory System Using Low-Speed DRAM Devices (Presentation)
  Hongzhong Zheng (University of Illinois at Chicago), Jiang Lin (IBM Corporation), Zhao Zhang (Iowa State University), Zhichun Zhu (University of Illinois at Chicago)


• Disaggregated Memory for Expansion and Sharing in Blade Servers (Presentation)
  Kevin Lim (University of Michigan), Jichuan Chang (Hewlett-Packard Laboratories) , Trevor Mudge (University of Michigan), Parthasarathy Ranganathan (Hewlett-Packard Laboratories), Steven K. Reinhardt (Advanced Micro Devices, Inc. and University of Michigan) , Thomas F. Wenisch (University of Michigan)


• The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization (Presentation)
  Cagdas Dirik, Bruce Jacob (University of Maryland)

Session 7A: Power in Chip Multiprocessors

• Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors (Presentation)
  Abhishek Bhattacharjee, Margaret Martonosi (Princeton University)


• Thread Motion: Fine-Grained Power Management for Multi-Core Systems
  Krishna K. Rangan (Harvard University and Intel Massachusetts) , Gu-Yeon Wei, David Brooks (Harvard University)


• Temperature-Constrained Power Control for Chip Multiprocessors with Online Model Estimation (Presentation)
  Yefu Wang, Kai Ma, Xiaorui Wang (University of Tennessee)

Session 7B: Hardware Support for Monitoring and Debugging

• A Case for an Interleaving Constrained Shared-Memory Multi-Processor (Presentation)
  Jie Yu, Satish Narayanasamy (University of Michigan)


• SigRace: Signature-Based Data Race Detection (Presentation)
  Abdullah Muzahid (University of Illinois at Urbana-Champaign), Dario Suárez (Universidad de Zaragoza), Shanxiang Qi, Josep Torrellas (University of Illinois at Urbana-Champaign)


• ECMon: Exposing Cache Events for Monitoring
  Vijay Nagarajan, Rajiv Gupta (University of California, Riverside)

Session 8A: Potpourri

• End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen (Presentation)
  Ali G. Saidi (The University of Michigan), Nathan L. Binkert (Hewlett-Packard Laboratories), Steven K. Reinhardt (Advanced Micro Devices), Trevor Mudge (The University of Michigan)


• Scaling the Bandwidth Wall: Challenges in and Avenues for CMP Scaling (Presentation)
  Brian M. Rogers (North Carolina State University), Anil Krishna, Gordon B. Bell, Ken Vu (IBM) , Xiaowei Jiang, Yan Solihin (North Carolina State University)


• A Fault Tolerant, Area Efficient Architecture for Shor's Factoring Algorithm (Presentation)
  Mark G. Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz (University of California, Berkeley)

Session 8B: Memory System Reconfiguration and Acceleration

• Performance and Power of Cache-Based Reconfigurable Computing (Presentation)
  Andrew Putnam, Susan Eggers (University of Washington) , Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig (Xilinx, Inc.)


• A Memory System Design Framework: Creating Smart Memories (Presentation)
  Amin Firoozshahian, Alex Solomatnikov (Hicamp Systems Inc.) , Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz (Stanford University)


• Flexible Reference-Counting-Based Hardware Acceleration for Garbage Collection (Presentation)
  José A. Joao (The University of Texas at Austin), Onur Mutlu (Carnegie Mellon University), Yale N. Patt (The University of Texas at Austin)

ISCA Outing to Oasis

Wednesday, June 24

Session 9: On-Chip Interconnection Networks

• Firefly: Illuminating Future Network-on-Chip with Nanophotonics (Presentation)
  Yan Pan, Prabhat Kumar (Northwestern University), John Kim (KAIST), Gokhan Memik, Yu Zhang, Alok Choudhary (Northwestern University)


• Phastlane: A Rapid Transit Optical Routing Network (Presentation)
  Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi (Cornell University)


• Achieving Predictable Performance through Better Memory Controller Placement in Many-Core CMPs
  Dennis Abts (Google Inc), Natalie D. Enright Jerger (University of Toronto), John Kim (KAIST), Dan Gibson, Mikko H. Lipasti (University of Wisconsin - Madison)

Session 10: Speculative Threading and Parallelization

• Dynamic Performance Tuning for Speculative Threads (Presentation)
  Yangchun Luo, Venkatesan Packirisamy, Wei-Chung Hsu, Antonia Zhai, Nikhil Mungre, Ankit Tarkas (University of Minnesota - Twin Cities)


• Boosting Single-thread Performance in Multi-core Systems through Fine-Grain Multi-Threading (Presentation)
  Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González (Intel Barcelona Research Center, & Universitat Politècnica de Catalunya)


• Simultaneous Speculative Threading: A Novel Pipeline Architecture Implemented in Sun's ROCK Processor (Presentation)
  Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay (Sun Microsystems, Inc.)